TTL inter-task communication implementation on a shared-memory multiprocessor platform

TTL is an abstract task-level interface which is used both for developing parallel application models and as a platform interface for implementing streaming applications on multi-processor architectures. Inter-task communication (ITC) is defined by TTL. The CAKE platform that we target, consists of homogeneous communicating tiles. Each tile consists of a shared memory with a heterogeneous mix of MIPS and TriMedia processors, DSPs and hardware accelerators. Due to task synchronization and data transfer in shared memory, architectural issues related with cache coherence and memory data copying are investigated. Optimizations such as padding-array insertion, prefetching and postflushing techniques are suggested. Alternative implemenations with semaphore and index/pointer as synchronization construct are explained. Prototype design and cycle true simulations with the Producer-Consumer model and the JPEG decoder application demonstrate that: compared to some old initial implementation, we can achieve almost 80% improvement on Cycles Per Token transfer (CPT), and reduce the total cycles of running the JPEG decoder application by 23%. Keywords—inter-task communication; synchronization; shared-memory multiprocessor; semaphore; cache coherence